Verify Operations Using Different Sense Node Voltages In A Memory Device

摘要

Sense circuits in a memory device can be pre-charged to different levels in a sensing process to reduce the amount of time used for sensing. For example, in a program operation, a memory cell is in a fast programming mode until its threshold voltage exceeds an offset verify voltage (VO) of a data state. The offset verify voltage is below a final verify voltage (VF) of the data state. When the threshold voltage is between VO and VF, the memory cell is in a slow programming mode. A verify test at VO for one memory cell can be performed concurrently with a verify test at VF for another memory cell by pre-charging a sense circuit for the one memory cell to a higher voltage than a sense circuit for the another memory cell. A common discharge period and trip condition can be used.

主权项

1. An apparatus, comprising:
a first sense circuit comprising a first sense node, the first sense circuit is associated with a first memory cell; a second sense circuit comprising a second sense node, the second sense circuit is associated with a second memory cell; and a control circuit, the control circuit is associated with the first sense circuit and with the second sense circuit and is configured to, in a sensing operation:
pre-charge the first sense node to a first sense node voltage;pre-charge the second sense node to a second sense node voltage which is lower than the first sense node voltage; andwhile a control gate voltage is applied to the first memory cell and the second memory cell, allow the first sense node voltage and the second sense node voltage to discharge in a discharge period.