| 发明名称 |
METAL ON BOTH SIDES WITH CLOCK GATED-POWER AND SIGNAL ROUTING UNDERNEATH |
| 摘要 |
A method including forming a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein the plurality of second interconnects include interconnects of different dimensions; and forming contact points to the second plurality of interconnects, the contact points operable for connection to an external source. An apparatus including a substrate including a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein the plurality of second interconnects include interconnects of different dimensions; and contact points coupled to the second plurality of interconnects, the contact points operable for connection to an external source. |
| 申请公布号 |
US2017077030(A1) |
申请公布日期 |
2017.03.16 |
| 申请号 |
US201415122913 |
申请日期 |
2014.09.27 |
| 申请人 |
Intel Corporation |
发明人 |
NELSON Donald W.;MORROW Patrick;JUN Kimin |
| 分类号 |
H01L23/528;H01L29/78;H01L23/00;H01L21/768 |
主分类号 |
H01L23/528 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method comprising:
forming a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer comprising a plurality of circuit devices, wherein the plurality of second interconnects include interconnects of different dimensions; and forming contact points to the second plurality of interconnects, the contact points operable for connection to an external source. |
| 地址 |
Santa Clara CA US |
