SEMICONDUCTOR ARRANGEMENT WITH CAPACITOR

摘要

A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory region also has a capacitor within one or more dielectric layers over the active region, where the capacitor is over the semiconductor device. The semiconductor arrangement also includes a protective ring within at least one of the logic region or the memory region and that separates the logic region from the memory region. The capacitor has a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, where the first electrode is substantially larger than other portions of the capacitor.

主权项

1. A method of forming a semiconductor arrangement, comprising:
etching a first opening in a first dielectric layer to expose a metal contact in a second dielectric layer underlying the first dielectric layer, wherein the metal contact provides an electrical connection through the second dielectric layer to a semiconductor device; etching a second opening in the first dielectric layer to expose a first portion of the second dielectric layer; forming a first conductive layer in the first opening and the second opening, wherein a portion of the first conductive layer in the first opening defines a first electrode and a portion of the first conductive layer in the second opening defines a protective ring; removing a portion of the first dielectric layer between the first electrode and the protective ring to expose a second portion of the second dielectric layer; and forming an insulating layer over the first electrode, the second portion of the second dielectric layer, and the protective ring.