Anti-fuse one-time programmable memory cell and anti-fuse one-time programmable memory array

摘要

An anti-fuse memory cell is provided. The anti-fuse memory cell includes a programmable transistor and a selection transistor. The programmable transistor includes a gate structure, a first doped region and a lightly doped region. The first doped region is divided into a first portion doped region, a second portion doped region and a third portion doped region. The first and second portion doped regions are respectively a source and a drain of the programmable transistor, and the third portion doped region is disposed between the first and second portion doped regions. The lightly doped region is distributed around a channel region of the programmable transistor, and adjacent to the first, second and third portion doped regions. The selection transistor includes a gate structure and a second doped region, and connected in series to the programmable transistor through the first portion doped region.

主权项

1. An anti-fuse one-time programmable memory cell, comprising:
a substrate; a well region, disposed on the substrate; a first programmable transistor, comprising:
a gate structure, disposed on the well region;a first doped region, divided into a first portion doped region, a second portion doped region and a third portion doped region, wherein the first, second and third portion doped regions are respectively disposed at three sides of the gate structure of the first programmable transistor and disposed in the well region; andwherein the first and second portion doped regions are respectively a source and a drain of the first programmable transistor, and the third portion doped region is disposed between the first and second portion doped regions; anda first lightly doped region, disposed in the well region, wherein the first lightly doped region is distributed around a channel region of the first programmable transistor and is respectively adjacent to the first, second and third portion doped regions; and a selection transistor, connected in series to the first programmable transistor through the first portion doped region and comprising a gate structure and a second doped region, wherein the gate structure of the selection transistor is electrically connected to a word line; and
wherein the first and second portion doped regions are respectively disposed on both sides of the gate structure of the selection transistor and the second doped region is electrically connected to a bit line.