发明名称 | Dual loop regulator circuit | ||
摘要 | The embodiments described herein relate to an improved regulator circuit technique having a dual-loop configuration with a current regulation loop to provide the transient response and a voltage regulation loop to provide accurate DC voltage regulation. The current regulation loop comprises a pass transistor, a current sensing transistor, a current summation circuit, and a series of current mirrors to provide a fast load transient response current. The voltage regulation loop includes an output voltage feedback network, an error amplifier, a compensation capacitor, and the current sensing transistor and is configured to provide accurate DC offset regulation to diminish output voltage errors introduced by the transient load currents. | ||
申请公布号 | US9588541(B1) | 申请公布日期 | 2017.03.07 |
申请号 | US201514928703 | 申请日期 | 2015.10.30 |
申请人 | QUALCOMM Incorporated | 发明人 | Ho Ngai Yeung;Guan Hua |
分类号 | G05F3/26 | 主分类号 | G05F3/26 |
代理机构 | Haynes and Boone, LLP | 代理人 | Haynes and Boone, LLP |
主权项 | 1. A regulator circuit comprising a current regulation loop and a voltage regulation loop, the current regulation loop comprising: a pass transistor having a first terminal coupled with an input of the regulator circuit and a second terminal coupled with an output of the regulator circuit; a current sensing transistor configured to sense a load current at a first terminal coupled with the output of the regulator circuit and to output a first loop current complementary to the load current from a second terminal of the current sensing transistor; a first current mirror circuit comprising a first transistor pair configured to receive the first loop current and to mirror the first loop current from input to output of the first current mirror circuit; a current summation circuit configured to subtract the first loop current at the output of the first current mirror circuit from a constant current provided by a current source to obtain a difference current; and at least a second current mirror circuit comprising a second transistor pair coupled with the current summation circuit and configured to convey the difference current multiplied by a factor to the pass transistor to provide a response current at the output of the regulator circuit. | ||
地址 | San Diego CA US |