发明名称 Single wire serial interface master module and method thereof for sampling data information
摘要 The present invention discloses a single wire serial interface (SSI) master module, including: a sample delay controlling unit, configured to send a delay instruction; the state machine unit, configured to wait, according to the delay instruction, for a delay period starting from a moment when an SSI master module completes sending the last bit of address information in a read operation frame, and then send a sample control signal to a selector unit; the selector unit, configured to enable a transmission channel with a sampling unit after receiving the sample control signal; and the sampling unit, configured to sample data information from an SSI slave module. In the present invention, the state machine unit delays sending the sample control signal, and the sampling unit is controlled to delay sampling the data information, which avoids a data reception error caused by slow discharging of an IO PAD.
申请公布号 US9588933(B2) 申请公布日期 2017.03.07
申请号 US201314089401 申请日期 2013.11.25
申请人 Huawei Technologies Co., Ltd. 发明人 Wang Qi
分类号 G06F13/00;G06F13/42;G06F13/40;G06F13/364;H04L12/403 主分类号 G06F13/00
代理机构 Leydig, Voit & Mayer, Ltd. 代理人 Leydig, Voit & Mayer, Ltd.
主权项 1. A single wire-serial interface_(SSI) master module comprising: a state machine unit; a selector unit; a sampling unit; and a sample delay controlling unit; wherein the sample delay controlling unit is connected to the state machine unit and is configured to send, before the SSI master module sends a last bit of address information in a first read operation each time after being power on or reset, a delay instruction to the state machine unit; wherein the state machine unit is connected to the selector unit and is configured to: wait, according to the delay instruction, for a delay period starting from a moment when the SSI master module completes sending the last bit of the address information in the read operation frame, wherein the delay period depends on a maximum delay for signal transmission on a side of the SSI master module and a maximum delay for signal transmission on a side of an SSI slave module, andsend a sample control signal to the selector unit; wherein the selector unit includes a first end connected to the sampling unit and a second end connected to the SSI slave module through a single wire, and is configured to, after receiving the sample control signal, enable a transmission channel between the selector unit and the sampling unit enable the SSI slave module to input data information corresponding to the address information in the read operation frame into the sampling unit; and wherein the sampling unit is configured to sample the data information from the SSI slave module.
地址 Shenzhen CN