Reduced-power trace array for a processor

摘要

A trace array having features that provide reduced power consumption/power dissipation in processor circuits. The trace array circuit stores processor states during program execution and provides a resulting trace for subsequent analysis. The trace array includes power management features that, responsive to a control signal, reduce the power consumption of the trace array. A first state of the control signal indicates that the trace array circuit is storing states during the execution of the program and a second state of the control signal is set to enable the trace array for reading the collected states. The trace array may have dynamic read bit-lines and static write bit-lines to further reduce power consumption, and the pre-charge circuits that charge the dynamic read bit-lines may be selectively disabled in response to the first state of the control signal. Write-through may also be selectively disabled and optionally bypassed during state collection.

主权项

1. A processor integrated circuit, comprising:
a plurality of functional units for executing program instructions; and at least one trace array coupled to at least one of the functional units for storing states of the at least one functional unit during execution of the program instructions, and providing a resulting trace for subsequent analysis of operation of the processor subsequent to the storing of the states, wherein the at least one trace array includes power management features responsive to a control signal that has a first state asserted during the execution of the program instructions and a second state asserted during an interval in which the program instructions are not being executed, whereby power consumption of the at least one trace array is reduced by the power management features.