发明名称 Flip chip stacking utilizing interposer
摘要 An interposer and a method for stacking dies utilizing such an interposer in an integrated circuit are disclosed. The interposer includes a substrate and a plurality of vias defined in the substrate. At least one of the plurality of vias of the interposer is positioned to establish a connection with at least one of the plurality of vias of a first die. At least one additional die is positioned to establish a connection with the first die utilizing the connection established between the interposer and the first die through at least one of the vias.
申请公布号 US9589913(B1) 申请公布日期 2017.03.07
申请号 US201313853232 申请日期 2013.03.29
申请人 Rockwell Collins, Inc. 发明人 Shepard Sarah M.;Simon Bret W.;Boone Alan P.
分类号 H01L23/48;H01L23/52;H01L29/40;H01L23/00;H01L21/82;H05K1/18;H01L25/065 主分类号 H01L23/48
代理机构 代理人 Gerdzhikov Angel N.;Suchy Donna P.;Barbieri Daniel M.
主权项 1. An integrated circuit, comprising: a flip chip die positioned on a circuit board, the flip chip die including a plurality of vertical interconnect accesses (vias), the flip chip die having an active side and a non-active side opposite to the active side, the active side of the flip chip die being oriented to face the circuit board; an interposer positioned on the flip chip die opposite to the circuit board, the interposer including a plurality of vias, wherein at least one of the plurality of vias of the interposer is positioned to establish a connection with at least one of the plurality of vias of the flip chip die; and a plurality of additional dies positioned directly on the interposer opposite to the flip chip die, wherein each of said plurality of additional dies is positioned to establish a connection with the same flip chip die utilizing said at least one of the plurality of vias of the interposer communicatively connected with said at least one of the plurality of vias of the flip chip die, and wherein the interposer is configured to provide routing between said plurality of additional dies and the same flip chip die to preserve signal integrity between said plurality of additional dies and the flip chip die.
地址 Cedar Rapids IA US