发明名称 EFFICIENT SHARING OF HARDWARE ENCRYPTION PIPELINE FOR MULTIPLE SECURITY SOLUTIONS
摘要 A processing or memory device may include a first encryption pipeline to encrypt and decrypt data with a first encryption mode and a second encryption pipeline to encrypt and decrypt data with a second encryption mode, wherein the first encryption pipeline and the second encryption pipeline share a single, shared pipeline for a majority of encryption and decryption operations performed by the first encryption pipeline and by the second encryption pipeline. A controller (and/or other logic) may direct selection of encrypted (or decrypted) data from the first and second encryption pipelines responsive to a region of memory to which a physical address of a memory request is directed. The result of the selection may result in bypassing encryption/decryption or encrypting/decrypting the data according to the first encryption mode or the second encryption mode. More than two encryption modes are envisioned.
申请公布号 US2017063532(A1) 申请公布日期 2017.03.02
申请号 US201514753987 申请日期 2015.06.29
申请人 Intel Corporation 发明人 Bhattacharyya Binata;Chhabra Siddhartha;Zhyvov Evgeny;Kishinevsky Eugene M.;Long Men
分类号 H04L9/06;G06F21/76;G06F21/72 主分类号 H04L9/06
代理机构 代理人
主权项 1. A processing device comprising: a first encryption pipeline to encrypt and decrypt data with a first encryption mode; a second encryption pipeline to encrypt and decrypt data with a second encryption mode; and wherein the first encryption pipeline and the second encryption pipeline share a single, shared pipeline for a majority of encryption and decryption operations performed by the first encryption pipeline and by the second encryption pipeline.
地址 Santa Clara CA US