发明名称 POWER MONITORING DEVICE AND RECEIVING APPARATUS
摘要 An APD that converts a received optical signal to a current signal, a current mirror circuit that duplicates the current signal and outputs a duplicate current signal as a mirror current, a resistor that converts the mirror current to a voltage, a sample and hold circuit that samples the converted voltage at a timing when a trigger voltage is input and holds a value of the sampled voltage, an inverter connected between the resistor and the sample and hold circuit, and a capacitor connected to the output side of the inverter are included, and the inverter allows the capacitor to be connected to the input side of the sample and hold circuit when a trigger voltage is input to the sample and hold circuit and allows the capacitor to be unconnected to the input side of the sample and hold circuit when the trigger voltage is not input to the sample and hold circuit.
申请公布号 US2017063452(A1) 申请公布日期 2017.03.02
申请号 US201415307979 申请日期 2014.06.05
申请人 Mitsubishi Electric Corporation 发明人 SHIRAI Satoshi;ASHIDA Tetsuro;NOGAMI Masamichi
分类号 H04B10/079;H04B10/69 主分类号 H04B10/079
代理机构 代理人
主权项 1. A power monitoring device, comprising: a photodetector that converts a received optical signal to a current signal; a current mirror circuit that duplicates the current signal and outputs the duplicated current signal as a mirror current; a current-to-voltage conversion circuit that converts the mirror current to a voltage; a sample and hold circuit that samples the voltage resulting from the conversion by the current-to-voltage conversion circuit at a timing when a trigger voltage is input and holds a value of the sampled voltage; a connection switching circuit connected between the current-to-voltage conversion circuit and the sample and hold circuit; and a capacitor connected to an output side of the connection switching circuit, wherein the connection switching circuit allows the capacitor to be connected to an input side of the sample and hold circuit when the trigger voltage is input to the sample and hold circuit and allows the capacitor to be unconnected to the input side of the sample and hold circuit when the trigger voltage is not input to the sample and hold circuit.
地址 Chiyoda-ku JP