LOAD STORE CIRCUIT WITH DEDICATED SINGLE OR DUAL BIT SHIFT CIRCUIT AND OPCODES FOR LOW POWER ACCELERATOR PROCESSOR

摘要

Described examples include integrated circuits such as microcontrollers with a low energy accelerator processor circuit or other application specific integrated processor circuit including a load store circuit operative to perform load and store operations associated with at least one register and a low gate count shift circuit to selectively shift the data of the register by only an integer number bits less than the register data width without using a barrel shifter for low power operation to support vector operations for FFT or filtering functions.

主权项

1. An integrated circuit, comprising:
a system bus; a first memory coupled with the system bus; a first processor circuit coupled to the system bus to execute instructions retrieved from the first memory; a second memory; an application specific integrated processor (ASIP) circuit coupled to the system bus to execute instructions retrieved from the second memory, the ASIP circuit including a load store circuit to store data from a memory location of the second memory to at least one register in the ASIP circuit; and a shift circuit operative according to an opcode of an instruction to selectively shift the data of the at least one register by one bit or two bits according to a single bit shift amount operand of the instruction.