发明名称 JUNCTIONLESS FIELD-EFFECT TRANSISTOR HAVING ULTRA-THIN LOW-CRYSTALLINE-SILICON CHANNEL AND FABRICATION METHOD THEREOF
摘要 A junctionless field-effect transistor is provided and has an ultra-thin low-crystalline silicon channel. A fabrication method thereof also is provided for enabling greatly improved economics by significantly reducing the process costs while having electrical characteristics similar to those of the one formed on an SOI substrate by source/channel/drain regions formed in a junctionless ultra-thin low-crystalline silicon layer that has lower crystallinity than that of single-crystal silicon and that has a thickness of 20 nm or less on a bulk silicon substrate instead of an expensive SOI substrate.
申请公布号 US2017062565(A1) 申请公布日期 2017.03.02
申请号 US201514969172 申请日期 2015.12.15
申请人 Gachon University of Industry-Academic cooperation Foundation 发明人 Cho Seongjae;Kim Youngmin
分类号 H01L29/10;H01L29/06;H01L29/08;H01L21/02;H01L21/324;H01L21/302;H01L29/66;H01L29/04;H01L29/16;H01L21/265;H01L29/423;H01L29/40 主分类号 H01L29/10
代理机构 代理人
主权项 1. A junctionless field-effect transistor comprising: a bulk silicon substrate; a silicon oxide layer formed on the silicon substrate; an ultra-thin junctionless low-crystalline silicon layer formed with a thickness of 20 nm or less on the silicon oxide layer; a gate electrode formed to be separated by a gate dielectric layer on the low-crystalline silicon layer; and source and drain electrodes formed with a specific interval from each other and separated by the gate electrode on the low-crystalline silicon layer, wherein the low-crystalline silicon layer is a polycrystalline silicon layer, the polycrystalline silicon under the gate electrode forming a channel region, and wherein the channel region has not any grain boundaries of the polycrystalline silicon in a length direction of the gate electrode.
地址 Seongnam-si KR