DUMMY GATE PLACEMENT METHODOLOGY TO ENHANCE INTEGRATED CIRCUIT PERFORMANCE

摘要

A method for increasing the performance of an integrated circuit by reducing the number of dummy gate geometries next to transistors in the speed path of an integrated circuit.

主权项

1. A process of forming an integrated circuit, comprising the steps:
laying out a transistor gate pattern with a transistor gate wherein the transistor gate is a critical gate in a speed path of the integrated circuit; laying out at least two dummy gate geometries adjacent to a first side of the critical gate; laying out at least two dummy gate geometries adjacent to a second side of the critical gate; placing a first dummy gate keep-out zone on the first side of the critical gate; placing a second dummy gate keep-out zone on the second side of the critical gate; and removing at least one dummy gate geometry from the first and the second dummy gate keep-out zones; saving the transistor gate pattern in a data base; forming a gate pattern photo mask using the transistor gate pattern; and printing the transistor gate pattern in photo resist on a wafer during manufacture of the integrated circuit.