MEMS AND CMOS INTEGRATION WITH LOW-TEMPERATURE BONDING

摘要

The present disclosure relates an integrated chip having one or more MEMS devices. In some embodiments, the integrated chip has a carrier substrate with one or more cavities disposed within a first side of the carrier substrate. A dielectric layer is disposed between the first side of the carrier substrate and a first side of a micro-electromechanical system (MEMS) substrate. The dielectric layer has sidewalls that are laterally set back from sidewalls of openings extending through the MEMs substrate to the one or more cavities. A bonding structure, including an intermetallic compound having a plurality of metallic elements, abuts a second side of the MEMS substrate and is electrically connected to a metal interconnect layer within a dielectric structure disposed over a CMOS substrate.

主权项

1. An integrated chip, comprising:
a carrier substrate comprising one or more cavities disposed within a first side of the carrier substrate; a dielectric layer disposed between the first side of the carrier substrate and a first side of a micro-electromechanical system (MEMS) substrate, wherein the dielectric layer has sidewalls that are laterally set back from sidewalls of openings extending through the MEMs substrate to the one or more cavities; and a bonding structure comprising an intermetallic compound having a plurality of metallic elements, wherein the bonding structure abuts a second side of the MEMS substrate and is electrically connected to a metal interconnect layer within a dielectric structure disposed over a CMOS substrate.