METHOD FOR MANUFACTURING A WAFER LEVEL PACKAGE

摘要

A method for fabricating a wafer level package is disclosed. A substrate having a top surface and a bottom surface is provided. A first dielectric layer is formed on the top surface. A redistribution layer (RDL) is formed on the first dielectric layer. The RDL comprises at least a second dielectric layer and at least a metal layer in the second dielectric layer. A first passivation layer is formed on the RDL. Bumps are formed in the first passivation layer. A chip is mounted on the RDL. The chip is electrically connected to the metal layer through the bumps. A molding compound is applied on the first passivation layer and around the chip. The bottom surface of the substrate is grinded until a remaining thickness of the substrate is reached. A plurality of through substrate vias is formed in the substrate.

主权项

1. A method for fabricating a wafer level package, comprising:
providing a substrate having a top surface and a bottom surface; forming a first dielectric layer on the top surface; forming a redistribution layer (RDL) on the first dielectric layer, wherein the RDL comprises at least a second dielectric layer and at least a metal layer in the second dielectric layer; forming a first passivation layer on the RDL; forming bumps in the first passivation layer; mounting a chip on the RDL, wherein the chip is electrically connected to the metal layer through the bumps; forming a molding compound on the first passivation layer and around the chip; after forming the molding compound to surround the chip, grinding the bottom surface of the substrate until a remaining thickness of the substrate is reached; and after grinding the bottom surface of the substrate until the remaining thickness of the substrate is reached, forming a plurality of through substrate vias in the substrate.