DEVICE AND PROCESSING ARCHITECTURE FOR INSTRUCTION MEMORY EFFICIENCY

摘要

Different processor architectures are described to evaluate and track dependencies required by instructions. The processors may hold or queue instructions that require output of other instructions until required data and resources are available which may remove the requirement of NOPs in the instruction memory to resolve dependencies and pipeline hazards. The processor may divide instruction data into bundles for parallel execution and provide speculative execution. The processor may include various components to implement an evaluation unit, execution unit and termination unit.

主权项

1. A processor comprising:
an instruction memory for storing instructions at corresponding instruction memory addresses, each instruction being a data structure that references operands and opcode; an instruction memory controller for controlling access to the instruction memory; an evaluation unit for triggering the instruction memory controller to receive instruction data from the instruction memory, evaluating operand and execution dependencies for the operands and the opcode of the instruction data, determining source register identifiers for source data for the operands of the instruction data and destination register identifiers for instruction results generated by execution of the instruction data, and evaluating resource requirements for the execution of the instruction data; an execution unit for dispatching the instruction data to computational resources for execution when the source data for the operands is ready or available and the resources specified by the resource requirements are ready or available; a termination unit for terminating the execution of the instruction when speculation is resolved and triggering transfer of the instruction results from temporary registers to the destination register; registers and a data memory for loading the source data required for the operands to execute the instruction data and receiving the instruction results generated by the execution of the instruction data; and a data memory controller for controlling access to the data memory for the source data and reading from and writing to the data memory based on the opcode of the instruction data and the instruction results.