| 摘要 |
Disclosed is an apparatus 200 with control circuitry 140 that receives a first N-bit count value 102 in a first domain, and to determines an M-bit difference indicating value, based on the first N-bit count value and a reference value 104, where M<N. Boundary circuitry 160 provides the M-bit difference indicating value to a second domain. In the second domain, updating circuitry 150 updates a second N-bit count value based on the difference represented by the M-bit difference indicating value provided by the boundary circuitry. The control circuitry may determine the M-bit difference indicating value as an update to be applied to a set of the least significant bits of the N-bit count value. The count value may be any value that counts the occurrences of some event in a processing system, eg a timestamp which counts the number of elapsed processing cycles, the number of executed instructions, number of exception events or interrupts of a given type, number of errors detected, number of accesses to given region of memory etc. |
