System and method for DDR memory timing acquisition and tracking

摘要

Systems, methods, and other embodiments associated with providing real time closed loop control of memory access are described. According to one embodiment, a method includes accessing a memory of a computing device during real time operation of the computing device and detecting bit errors associated with the accessing of the memory. The method also includes generating a performance metric based on, at least in part, the detected bit errors during the real time operation of the computing device. The method further includes adjusting a setting of at least one timing element, of a plurality of timing elements of a physical layer of the computing device, based on the performance metric during the real time operation of the computing device to maintain a determined memory access performance.

主权项

1. An apparatus comprising:
memory configured to be accessed by having data written thereto and read therefrom; memory control logic configured to control memory access of the memory via a plurality of signal lines; physical layer logic configured to provide a tunable signal interface for the plurality of signal lines between the memory control logic and the memory; and performance monitor logic configured to provide closed loop control, to maintain a determined apparatus performance associated with the memory access, by:
(i) detecting bit errors associated with the memory access during real time operation of the apparatus,(ii) generating a performance metric based on, at least in part, the detected bit errors during the real time operation of the apparatus, and(iii) tuning a signal parameter of at least one signal associated with at least one signal line of the plurality of signal lines via the physical layer logic based on, at least in part, the performance metric during the real time operation of the apparatus.