发明名称 |
Memory device and method for manufacturing the same |
摘要 |
A memory device having an array area and a periphery area is provided. The memory device includes a substrate, an isolation layer formed in the substrate, a first doped region formed on the isolation layer in the array area, a second doped region formed on the first doped region, a metal silicide layer formed on the second doped region, and a metal silicide oxide layer formed on the metal silicide layer. |
申请公布号 |
US9583536(B2) |
申请公布日期 |
2017.02.28 |
申请号 |
US201514806832 |
申请日期 |
2015.07.23 |
申请人 |
MACRONIX INTERNATIONAL CO., LTD. |
发明人 |
Lai Erh-Kun;Wu Chao-I;Lin Yu-Hsuan;Lee Dai-Ying |
分类号 |
H01L47/00;H01L27/24;H01L45/00 |
主分类号 |
H01L47/00 |
代理机构 |
McClure, Qualey & Rodack, LLP |
代理人 |
McClure, Qualey & Rodack, LLP |
主权项 |
1. A memory device having an array area and a periphery area, comprising:
a substrate; an isolation layer formed in the substrate; a first doped region formed on the isolation layer in the array area; a second doped region formed on the first doped region; a first metal silicide layer formed on the second doped region; a metal silicide oxide layer formed on the first metal silicide layer; a P-well formed in the substrate in the periphery area; a N-well formed adjacent to the P-well in the periphery area; two first electrodes formed in the P-well; a first gate oxide layer formed on the P-well; two second electrodes formed in the N-well; a second gate oxide layer formed on the N-well; a first doped polysilicide layer formed on the first gate oxide layer; a second doped polysilicide layer formed on the second gate oxide layer; and a plurality of second metal silicide layers formed on the first doped polysilicide layer and the second doped polysilicide layer; wherein portions of the isolation layer is formed between the P-well and the N-well. |
地址 |
Hsinchu TW |