Integrated circuit power reduction through charge

摘要

Techniques for charge reuse in an integrated circuit. A processor may include a first logic circuit coupled to a source power supply node, a second logic circuit coupled to a destination power supply node, and a charge reuse circuit that selectively transfers charge from the first logic circuit to the second logic circuit. The charge reuse circuit may include an equalization device that selectively couples the source power supply node to the destination power supply node, and an equalization activation circuit that activates the equalization device in response to detecting assertion of an equalization control signal and further detecting that a voltage differential between the source power supply node and the destination power supply node is above a threshold value. The equalization activation circuit also prevents coupling of either the source power supply node or the destination power supply node to ground during activation of the equalization device.

主权项

1. An integrated circuit, comprising:
a source power supply node configured to supply power to a first logic circuit; a destination power supply node configured to supply power to a second logic circuit; an equalization device configured to selectively couple the source power supply node to the destination power supply node; a pulldown network coupled to receive an equalization control signal, a source node input, and a destination node input and configured to selectively activate the equalization device; a source node control circuit coupled to the source power supply node and receiving an inverted version of the equalization control signal and configured to generate the source node input to the pulldown network; and a destination node control circuit coupled to the destination power supply node and receiving the inverted version of the equalization control signal and configured to generate the destination node input to the pulldown network, wherein: a control input of the source node control circuit is coupled to the destination power supply node; a control input of the destination node control circuit is coupled to the source power supply node; and the source node control circuit, the destination node control circuit, the pulldown network, and the equalization device are collectively configured to cause charge to transfer between the source power supply node and the destination power supply node in response to assertion of the equalization control signal.