发明名称 |
Quantum efficiency of multiple quantum wells |
摘要 |
Improved quantum efficiency of multiple quantum wells. In accordance with an embodiment of the present invention, an article of manufacture includes a p side for supplying holes and an n side for supplying electrons. The article of manufacture also includes a plurality of quantum well periods between the p side and the n side, each of the quantum well periods includes a quantum well layer and a barrier layer, with each of the barrier layers having a barrier height. The plurality of quantum well periods include different barrier heights. |
申请公布号 |
US9583671(B2) |
申请公布日期 |
2017.02.28 |
申请号 |
US201514629487 |
申请日期 |
2015.02.23 |
申请人 |
Invensas Corporation |
发明人 |
Wang Liang;Mohammed Ilyas;Beroz Masud |
分类号 |
H01L21/00;H01L33/00;H01L33/06;H01L31/0352;H01L31/105;B82Y20/00;H01L33/32;H01L33/62;H01L29/06;H01L31/00;H01L33/24;H01S5/20;H01S5/34;H01S5/343;H01S5/32 |
主分类号 |
H01L21/00 |
代理机构 |
Forefront IP Lawgroup of Christie & Rivera, pllc |
代理人 |
Forefront IP Lawgroup of Christie & Rivera, pllc |
主权项 |
1. A method comprising:
forming a stack of layers for a multiple quantum well semiconductor device on a substrate, said stack of layers comprising: a p type layer; an electron blocking layer in contact with said p type layer; a plurality of quantum well periods in contact with said electron blocking layer, each of said quantum well periods comprising a quantum well layer and a barrier layer that comprises a barrier layer p type doping concentration, and wherein said plurality of quantum well periods comprise barrier layers of varying p type doping concentration; an n-type layer in contact with said plurality of quantum well periods; and etching said stack of layers such that said plurality of quantum well periods comprise said quantum well layers of varying area. |
地址 |
San Jose CA US |