Display device

摘要

By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an AC pulse. A shift in threshold voltage of a transistor which easily deteriorates and a shift in threshold voltage of a turned-on transistor are suppressed by signal input to a gate electrode of the transistor which easily deteriorates through the turned-on transistor. In other words, a structure for applying an AC pulse to a gate electrode of a transistor which easily deteriorates through a transistor to a gate electrode of which a high potential (VDD) is applied, is included.

主权项

1. A semiconductor device comprising:
a first flip-flop; and a second flip-flop, wherein the first flip-flop comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a first capacitor, wherein the second flip-flop comprises a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a second capacitor, wherein a ratio of a channel width to a channel length of the first transistor is greater than a ratio of a channel width to a channel length of the third transistor, wherein the ratio of the channel width to the channel length of the first transistor is greater than a ratio of a channel width to a channel length of the fifth transistor, wherein the ratio of the channel width to the channel length of the first transistor is greater than a ratio of a channel width to a channel length of the sixth transistor, wherein a ratio of a channel width to a channel length of the seventh transistor is greater than a ratio of a channel width to a channel length of the ninth transistor, wherein the ratio of the channel width to the channel length of the seventh transistor is greater than a ratio of a channel width to a channel length of the eleventh transistor, wherein the ratio of the channel width to the channel length of the seventh transistor is greater than a ratio of a channel width to a channel length of the twelfth transistor, wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor, wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor, wherein one of a source and a drain of the fifth transistor is directly connected to one of a source and a drain of the sixth transistor, wherein a gate of the first transistor is electrically connected to the one of the source and the drain of the fifth transistor, wherein a gate of the second transistor is directly connected to the one of the source and the drain of the fourth transistor, wherein the gate of the second transistor is directly connected to a gate of the sixth transistor, wherein a gate of the fourth transistor is directly connected to a gate of the fifth transistor, wherein the gate of the fourth transistor is directly connected to the other of the source and the drain of the fifth transistor, wherein a first electrode of the first capacitor is directly connected to the gate of the first transistor, wherein a second electrode of the first capacitor is directly connected to the one of the source and the drain of the first transistor, wherein one of a source and a drain of the seventh transistor is directly connected to one of a source and a drain of the eighth transistor, wherein one of a source and a drain of the ninth transistor is electrically connected to one of a source and a drain of the tenth transistor, wherein one of a source and a drain of the eleventh transistor is directly connected to one of a source and a drain of the twelfth transistor, wherein a gate of the seventh transistor is electrically connected to the one of the source and the drain of the eleventh transistor, wherein a gate of the eighth transistor is directly connected to the one of the source and the drain of the tenth transistor, wherein the gate of the eighth transistor is directly connected to a gate of the twelfth transistor, wherein a gate of the tenth transistor is directly connected to a gate of the eleventh transistor, wherein the gate of the tenth transistor is directly connected to the other of the source and the drain of the eleventh transistor, wherein a first electrode of the second capacitor is directly connected to the gate of the seventh transistor, wherein a second electrode of the second capacitor is directly connected to the one of the source and the drain of the seventh transistor, wherein the other of the source and the drain of the first transistor is directly connected to a first wiring, wherein the other of the source and the drain of the third transistor is directly connected to a second wiring, wherein the other of the source and the drain of the seventh transistor is directly connected to the second wiring, wherein the other of the source and the drain of the ninth transistor is directly connected to the first wiring, and wherein the one of the source and the drain of the first transistor is directly connected to the gate of the eleventh transistor.