发明名称 Multi-core programming apparatus and method for restoring data arrays following a power gating event
摘要 An apparatus includes a device programmer and a plurality of cores. The programmer programs a semiconductor fuse array with compressed configuration data. Each of the plurality of cores accesses the fuse array upon power-up/reset to read and decompress the compressed data, and stores decompressed data sets for one or more cache memories within the each of the plurality of cores in a stores that is coupled to the each of the plurality of cores. Each of the plurality of cores has reset logic and sleep logic. The reset logic employs the decompressed data sets to initialize the one or more cache memories upon power-up/reset. The sleep logic determines that power is restored following a power gating event, and subsequently accesses the stores to retrieve and employ the decompressed data sets to initialize the one or more caches following the power gating event.
申请公布号 US9582428(B2) 申请公布日期 2017.02.28
申请号 US201414889843 申请日期 2014.12.12
申请人 VIA ALLIANCE SEMICONDUCTOR CO., LTD. 发明人 Henry G. Glenn;Jain Dinesh K.;Gaskins Stephan
分类号 G06F12/08;G11C17/16;G06F1/32;G06F12/12;G06F9/445;G06F15/177;G11C7/20;G11C17/18;G06F9/44;G11C29/44 主分类号 G06F12/08
代理机构 代理人 Huffman Richard K.;Huffman James W.
主权项 1. An apparatus for providing configuration data to an integrated circuit, the apparatus comprising: a device programmer, coupled to a semiconductor fuse array disposed on a die, configured to program said semiconductor fuse array with compressed configuration data; and a plurality of cores, disposed on said die, wherein each of said plurality of cores is coupled to said semiconductor fuse array, and wherein one of said plurality of cores is configured to access said semiconductor fuse array upon power-up/reset to read and decompress said compressed configuration data, and to store decompressed configuration data sets for one or more cache memories within said each of said plurality of cores in a stores that is coupled to said each of said plurality of cores, said each of said plurality of cores comprising: reset logic, configured to employ said decompressed configuration data sets to initialize said one or more cache memories upon power-up/reset; andsleep logic, configured to determine that power is restored following a power gating event, and configured to subsequently access said stores to retrieve and employ said decompressed configuration data sets to initialize said one or more caches following said power gating event.
地址 Shanghai CN