发明名称 Al-poor barrier for InGaAs semiconductor structure
摘要 The present disclosure relates to a semiconductor structure and a method of preparation including a silicon monocrystalline substrate, and a III-V structure abutting the silicon monocrystalline substrate. The semiconductor structure includes an InaGabAs structure overlaying the III-V structure, where a is from 0.40 to 1, b from 0 to 0.60, and a+b equal to 1.00. The III-V structure has a top surface facing away from the silicon substrate. The top surface is GagXxPpSbsZz, where X includes one or more group III elements other than Ga and Z is one or more group V elements other than P or Sb. g is from 0.80 to 1.00, x is from 0 to 0.20, z is from 0 to 0.30, p is from 0.10 to 0.55, and s is from 0.50 to 0.80, g+x is equal to 1.00 and p+s+z is equal to 1.00.
申请公布号 US2017054021(A1) 申请公布日期 2017.02.23
申请号 US201615208783 申请日期 2016.07.13
申请人 IMEC VZW 发明人 Kunert Bernardette;Langer Robert
分类号 H01L29/78;H01L29/06;H01L29/423;H01L29/04;H01L29/205 主分类号 H01L29/78
代理机构 代理人
主权项 1. A semiconductor structure comprising: a) a Si monocrystalline substrate; b) a III-V structure abutting the Si monocrystalline substrate; and c) an InaGabAs structure overlaying the III-V structure, wherein a is from 0.40 to 1, b is from 0 to 0.60, and a+b is 1.00, wherein the III-V structure has a top surface facing away from the Si monocrystalline substrate, the top surface having a chemical composition GagXxPpSbsZz, wherein X is one or more group III elements other than Ga, wherein Z is one or more group V elements other than P or Sb, wherein g is from 0.80 to 1.00, x is from 0 to 0.20, z is from 0 to 0.30, p is from 0.10 to 0.55, and s is from 0.50 to 0.80, g+x is equal to 1.00 and p+s+z is equal to 1.00.
地址 Leuven BE