MULTIPLE-HOT (MULTI-HOT) BIT DECODING IN A MEMORY SYSTEM FOR ACTIVATING MULTIPLE MEMORY LOCATIONS IN A MEMORY FOR A MEMORY ACCESS OPERATION

摘要

Multiple-hot (multi-hot) bit decoding in a memory system for activating multiple memory locations in a memory for a memory access operation are disclosed. In one aspect, a multi-hot bit decoding system is provided that includes a memory access control system that includes a decoder. The decoder is configured to decode an address for a memory access operation into a single-hot bit decode word for activating a memory row at the encoded address. To automatically access another memory row(s) for a memory access operation, the memory access control system also includes a mapping circuit configured to provide an additional decode word(s) for activating another memory row(s) based on the address. The decode word and additional decode word(s) are merged to provide a multi-hot bit decode word that is asserted onto a decode wordline such that multiple memory rows are activated for a memory access operation.

主权项

1. A multiple-hot (multi-hot) bit decoding system for activating memory locations in a memory for a memory access operation, comprising:
a decoder configured to receive an encoded address for a memory access operation and decode the encoded address into a single-hot bit decode word corresponding to a memory row among a plurality of memory rows in a memory array corresponding to the encoded address; a mapping circuit configured to translate the single-hot bit decode word into one or more additional single-hot bit decode words corresponding to one or more other memory rows among the plurality of memory rows in the memory array not corresponding to the encoded address; and a merge circuit configured to merge the single-hot bit decode word and the one or more additional single-hot bit decode words into a multi-hot bit decode word asserted onto a multi-hot bit decode wordline configured to be accessed by a memory row access system to activate two or more memory rows among the plurality of memory rows based on the multi-hot bit decode word on the multi-hot bit decode wordline.