| 发明名称 |
SINGLE SYNCHRONOUS FIFO IN A UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER SYSTEM |
| 摘要 |
A UART device includes a glue logic configured to receive data from either a computer processing unit (CPU) interface of the UART device or from a receiver interface of the UART device; determine whether the data was received from the CPU interface or the receiver interface; and add a most significant bit (MSB) to the data. A value of the MSB is based on whether the data was received from the CPU interface or the receiver interface. The UART device may write the data with the added MSB to a data buffering and storage component. |
| 申请公布号 |
US2017054578(A1) |
申请公布日期 |
2017.02.23 |
| 申请号 |
US201514832016 |
申请日期 |
2015.08.21 |
| 申请人 |
King Abdulaziz City for Science and Technology |
发明人 |
Obeid Abdulfattah Mohammad;BenSaleh Mohammed Sulaiman;AlJuffri Abdullah Alawi;Qasim Syed Manzoor |
| 分类号 |
H04L25/05 |
主分类号 |
H04L25/05 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method comprising:
receiving data from either a computer processing unit (CPU) interface of a computing device or from a receiver interface; determining whether the data was received from the CPU interface or the receiver interface; adding a most significant bit (MSB) to the data, wherein a value of the MSB is based on whether the data was received from the CPU interface or the receiver interface; and writing the data with the added MSB to a data buffering and storage component. |
| 地址 |
Riyadh SA |
