| 摘要 |
Flexible, space-efficient I/O architectures for integrated circuits simplify circuit design and shorten design times. In one aspect, cells for power supply pads are eliminated, in part by locating ESD circuitry for these pads underneath the pads themselves, leaving only signal I/O buffers. Pads coupled to the signal I/O buffers may be defined as either signal I/O pads or power supply pads in accordance with customization circuitry. Customization circuitry also provides for flexible bank architectures, where signal I/O buffers within a bank share power supply requirements that may be different from another bank. The number of banks and the number of signal I/O buffers belonging to each bank is flexibly defined. In other aspects, ESD circuitry is provided at corners of the IC layout and optionally within selected I/O slots. Decap circuitry is provided at an outer edge of the IC layout and is scalable in order to meet different requirements. |
| 主权项 |
1. A metal programmable integrated circuit comprising a core logic region and a surrounding I/O region, the I/O region comprising tiled cells defining:
a plurality of ranks of I/O slots surrounding the core logic region; a plurality of power strap segment segments surrounding the core logic region; multiple tiers of pads surrounding the core logic region and grouped into groups of pads, pads of different tiers being staggered relative to pads of at least one other tier, wherein for each of a plurality of the groups of pads, the group of pads is positioned adjacent to or above a group of I/O slots having a fewer number of I/O slots than a number of pads in the group of pads, and the group of pads has a width not greater than a width of the group of I/O slots; a plurality of power clamp circuits; and one or more programmable metal layers coupling each of the power clamp circuits to one of the power strap segment segments and to at least one of the pads; wherein the one or more programmable metal layers determine at least one of: pad definitions of a plurality of pads as between at least signal pads, power pads of a first voltage, power pads of a second voltage, and ground pads; and power bank definitions of a plurality of power banks, each power bank having a span that spans a range of pads, wherein for each power bank at least one of said power strap segment segments is continuous across a span of that power bank; and wherein for each I/O slot of the plurality of ranks of I/O slots, each of the plurality of power strap segment segments, and each of the pads of the plurality of groups of pads, different I/O slots are defined by identical cells, different power strap segment segments are defined by identical cells, and different pads are defined by identical cells. |
