Programmable address-based write-through cache control

摘要

This invention is a cache system with a memory attribute register having plural entries. Each entry stores a write-through or a write-back indication for a corresponding memory address range. On a write to cached data the cache the cache consults the memory attribute register for the corresponding address range. Writes to addresses in regions marked as write-through always update all levels of the memory hierarchy. Writes to addresses in regions marked as write-back update only the first cache level that can service the write. The memory attribute register is preferably a memory mapped control register writable by the central processing unit.

主权项

1. A data processing method comprising the steps of:
storing a plurality of memory attributes for a corresponding memory address range in a memory attribute register having plural entries, said memory attributes including a write-through enable (WTE) bit indicating a write-through or a write-back for said corresponding memory address range; temporarily storing in a plurality of cache lines of a first data cache data for manipulation by said central processing unit; temporarily storing in a plurality of cache lines in a second level memory including a second level cache data for manipulation by said central processing unit; upon a central processing unit write to data cached in said first data cache
writing said data in a corresponding cache line in said first data cache and passing said data on to write base memory if said write-through enable (WTE) bit of said memory attribute register entry for an address of said central processing unit write indicates write-through, andwriting said data in a corresponding cache line in said first data cache and not passing said data on to write in base memory if said write-through enable (WTE) bit of said memory attribute register entry for an address of said central processing unit write indicates write-back; and upon a central processing unit write to data cached in said second level cache
writing said data in a corresponding cache line in said second level cache if said write-through enable (WTE) bit of said memory attribute register entry for an address of said central processing unit write indicates write-through,writing said data in a corresponding cache line in said second level cache if said write-through enable (WTE) bit of said memory attribute register entry for an address of said central processing unit write indicates write-back and said data is not cached in said first data cache, andnot writing said data in a corresponding cache line in said second level cache if said write-through enable (WTE) bit of said memory attribute register entry for an address of said central processing unit write indicates write-back and said data is cached in said first data cache; and locating said write-through enable (WTE) bit of each entry of said memory attribute register at a data memory controller for said first data cache; and locating at least one of said plurality of memory attributes of each entry of said memory attribute register at a unified memory controller for said second level memory.