RRAM cell with PMOS access transistor

摘要

The present disclosure relates to an integrated chip comprising an RRAM cell that is driven by a PMOS transistor, and an associated method of formation. In some embodiments, the integrated chip has a PMOS transistor arranged within a semiconductor substrate. A resistive RRAM cell is arranged within an inter-level dielectric (ILD) layer overlying the semiconductor substrate. The RRAM cell has a first conductive electrode separated from a second conductive electrode by a dielectric data storage layer having a variable resistance. The first conductive electrode is connected to a drain terminal of the PMOS transistor by one or more metal interconnect layers. The use of a PMOS transistor to drive the RRAM cell allows for impact of the body effect to be reduced and therefore allows for a reset operation to be performed at a low power and in a short amount of time.

主权项

1. A method of forming an integrated chip, comprising:
forming a PMOS transistor within a substrate; forming a resistive random access memory (RRAM) cell over the substrate, wherein the RRAM cell has a first conductive electrode that is connected to a drain terminal of the PMOS transistor and that is separated from a second conductive electrode by a dielectric data storage layer having a variable resistance, wherein forming the RRAM cell comprises: forming a bottom dielectric layer over an ILD layer overlying the substrate; sequentially depositing a bottom electrode layer, a dielectric data storage layer, a top electrode layer, and a hard mask layer; etching the bottom electrode layer, the dielectric data storage layer, and the top electrode layer to form a bottom electrode, a dielectric data storage layer, and a top electrode, wherein the bottom electrode comprises a lower portion surrounded by the bottom dielectric layer and an upper portion; forming a top dielectric layer over the top electrode and the bottom dielectric layer; forming an upper ILD layer over the top dielectric layer; wherein the lower portion has curved sidewalls that cause a lower width of the bottom electrode to decrease as a distance from the substrate decreases, and the upper portion has angled sidewalls that cause an upper width of the bottom electrode to decrease as a distance from the substrate increases; wherein a bottom surface of the bottom electrode has a smaller width than a top surface of the bottom electrode; and wherein the PMOS transistor is configured to be turned on while a non-zero bias voltage is applied to a bulk terminal of the PMOS transistor to perform a reset operation on the RRAM cell.