| 摘要 |
In some examples, a circuit is described. The circuit may be included in a digital phase-locked loop (PLL) and may include a first delay cell, a second delay cell, and a delay controller. The first delay cell may include a first inverter circuit that includes first and second transistors and may be configured to receive and to delay a first signal. The delay of the first inverter circuit may be based on first and second voltages respectively provided to the first and second transistors. The second delay cell may include a second inverter circuit that includes third and fourth transistors and may be configured to receive and to delay a second signal. The delay of the second inverter circuit may be based on third and fourth voltages respectively provided to the third and fourth transistors. The delay controller may be configured to provide the first, second, third, and fourth voltages. |
| 主权项 |
1. A circuit, comprising:
a first delay cell that includes a first inverter circuit, wherein the first inverter circuit includes first and second transistors, the first delay cell is configured to receive and to delay a first signal based on a first delay of the first inverter circuit and to output the delayed first signal, and the first delay of the first inverter circuit is based on first and second voltages respectively provided to the first and second transistors, wherein the first and second voltages are different; a second delay cell that includes a second inverter circuit, wherein the second inverter circuit includes third and fourth transistors, the second delay cell is configured to receive and to delay a second signal based on a second delay of the second inverter circuit and to output the delayed second signal, and the second delay of the second inverter circuit is based on third and fourth voltages respectively provided to the third and fourth transistors, wherein the third and fourth voltages are different; and a delay controller coupled to the first delay cell and the second delay cell, the delay controller configured to provide the first, second, third, and fourth voltages, wherein the first, second, third, and fourth voltages are configured such that the first delay is different in duration than the second delay. |
