发明名称 |
EMBEDDED LOGIC ANALYZER AND INTEGRATED CIRCUIT INCLUDING THE SAME |
摘要 |
An embedded logic analyzer of an integrated circuit includes a comparison block configured to generate a capture data signal and a plurality of comparison enable signals based on an input data signal from one of function blocks included in the integrated circuit such that the comparison enable signals are activated respectively based on different comparison conditions; an operation block configured to perform a logic operation on the comparison enable signals to generate a data enable signal indicating a data capture timing; and packer circuitry configured to generate a packer data signal including capture data and capture time information based on the capture data signal, the data enable signal and a time information signal. |
申请公布号 |
US2017045582(A1) |
申请公布日期 |
2017.02.16 |
申请号 |
US201615170020 |
申请日期 |
2016.06.01 |
申请人 |
Samsung Electronics Co., Ltd. |
发明人 |
KO JOON-WON |
分类号 |
G01R31/317;G01R31/3177;H03K5/26;H03K19/173;H03K19/177 |
主分类号 |
G01R31/317 |
代理机构 |
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代理人 |
|
主权项 |
1. An embedded logic analyzer of an integrated circuit, comprising:
a comparison block configured to generate a capture data signal and a plurality of comparison enable signals based on an input data signal from one of function blocks included in the integrated circuit such that the comparison enable signals are activated respectively based on different comparison conditions; an operation block configured to perform a logic operation on the comparison enable signals to generate a data enable signal indicating a data capture timing; and packer circuitry configured to generate a packer data signal including capture data and capture time information based on the capture data signal, the data enable signal and a time information signal. |
地址 |
Suwon-si KR |