Robust gate spacer for semiconductor devices

摘要

After formation of a gate structure and a lower dielectric spacer laterally surrounding the gate structure, a disposable material layer is deposited and planarized such that the top surface of the disposable material layer is formed below the topmost surface of the lower dielectric spacer. An upper dielectric spacer is formed around the gate structure and over the top surface of the disposable material layer. The disposable material layer is removed selective to the upper and lower dielectric spacers and device components underlying the gate structure. Semiconductor surfaces of the gate structure can be laterally sealed by the stack of the lower and upper dielectric spacers. Formation of any undesirable semiconductor deposition on the gate structure can be avoided by the combination of the lower and upper dielectric spacers during a subsequent selective epitaxy process.

主权项

1. A semiconductor structure comprising:
a semiconductor material portion located on a substrate; a gate structure including a stack, from bottom to top, of a gate dielectric, a gate electrode, and a gate dielectric cap, and straddling said semiconductor material portion; a lower dielectric spacer laterally contacting, and surrounding an entire outermost vertical surface of said gate electrode and a first portion of said gate dielectric cap; an upper dielectric spacer comprising a first portion laterally contacting and surrounding a second portion of said gate dielectric cap, and a second portion of said upper dielectric spacer contacting an outermost surface of said lower dielectric spacer; and a contact level dielectric layer having a topmost surface that is located above a topmost surface of said gate structure and a bottommost surface that is coplanar with a bottommost surface of said semiconductor material portion, wherein a portion of said contact level dielectric layer is in direct contact with an entire outermost surface and an uppermost surface of said upper dielectric spacer, and another portion of said contact level dielectric layer is in direct contact with a planar bottom surface of said upper dielectric spacer.