On-die termination of address and command signals

摘要

A system has a plurality of memory devices arranged in a fly-by topology, each having on-die termination (ODT) circuitry for connecting to an address and control (RQ) bus. The ODT circuitry of each memory device includes a set of one or more control registers for controlling on-die termination of one or more signal lines of the RQ bus. A first memory device includes a first set of one or more control registers storing a first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the first memory device, and a second memory device includes a second set of one or more control registers storing a second ODT value different from the first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the second memory device.

主权项

1. A memory controller configured to be connected to a memory device via a command and address bus, wherein the memory device includes on-die termination (ODT) circuitry connected to at least a subset of signal lines of the command and address bus, the memory controller comprising a circuit to transmit command and address signals to the memory device, the memory controller further configured to set register values in the memory device, the register values including a register value to specify an ODT impedance to be applied by the ODT circuitry.