Using dynamic bursts to support frequency-agile memory interfaces

摘要

The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.

主权项

1. A method for operating a memory controller, comprising:
for at least one change in a host processor host-to-memory-controller interface instantaneous data rate from a first data rate R1 to a relatively slower data rate R2, decreasing an average data rate of a memory interface of a memory controller substantially proportional to R2/R1 without a proportional decrease in an instantaneous data rate of the memory interface by operating the memory interface in a burst mode; wherein the burst mode comprises interspersing low-power intervals on the memory interface between at least some memory requests corresponding to temporally adjacent host requests; and wherein the low-power intervals comprise turning off a memory clock signal supplied by the memory interface.