Distributed timer subsystem across multiple devices

摘要

Multiple ARM devices, each having multiple processing elements, linked together by an interconnect to form a coherent memory fabric in which each device has access to all of the processing elements located on all of the devices that are part of the coherent memory fabric. In order to comply with the ARM architecture, the system must have a global timer that is accessible to all of the ARM devices so that each of the devices can maintain the same timer value. The devices, systems, and methods disclosed herein provide for initial synchronization between multiple ARM devices that are joined together to form a coherent memory fabric. The initial synchronization is achieved by determining an offset between the timers of each ARM device and then minimizing the offset. The synchronization may be periodically checked and adjusted, as necessary, to maintain proper synchronization.

主权项

1. An apparatus comprising:
a first silicon device configured in accordance with an Advanced RISC Machines™ (ARM) architecture, the first silicon device having a timer and at least one processing element; a second silicon device configured in accordance with the ARM architecture, the second silicon device having a timer and at least one processing element; an interconnect coupled between the first silicon device and the second silicon device such that both the first and second silicon devices have access to any of the processing elements disposed on both the first and second silicon devices; and at least one of the first and second silicon devices configured to determine an offset between the timer of the first silicon device and the timer of the second silicon device in accordance with a total delay of a first synchronization message transmitted from the first silicon device to the second silicon device and a total delay of a second time synchronization message transmitted from the second silicon device to the first silicon device.