Memory refresh method and devices

摘要

The present disclosure describes DRAM architectures and refresh controllers that allow for scheduling of an opportunistic refresh of a DRAM device concurrently with normal row activate command directed toward the DRAM device. Each activate command affords an “opportunity” to refresh another independent row (i.e., a wordline) within a memory device with no scheduling conflict.

主权项

1. A memory comprising:
a stack of dynamic random access memory (DRAM) dies, each DRAM including a plurality of banks, each of the plurality of banks having a plurality of memory cells; a buffer circuit configured to:
receive a first activate command and a first data access command; andresponsive to receiving the first activate command and the first data access command, provide:
a first bank address, wherein the first bank address identifies a first bank of the plurality of banks in the stack;a first row address that identifies a row of memory cells within the first bank of the stack for a memory access;a second bank address, wherein the second bank address identifies a second bank of the plurality of banks in the stack; anda second row address that identifies a row of memory cells within the second bank of the stack to perform a refresh operation; and a first interface connected to the buffer circuit, the first interface to receive the first bank address, the second bank address, the first row address, and the second row address from the buffer circuit and output the first bank address, the second bank address, the first row address, and the second row address to the stack; wherein the row of memory cells within the first bank is sensed while the row of memory cells in the second bank is refreshed.