发明名称 Method of semiconductor integrated circuit fabrication
摘要 A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.
申请公布号 US9570347(B2) 申请公布日期 2017.02.14
申请号 US201514733487 申请日期 2015.06.08
申请人 Taiwan Semiconductor Manufacturing Company, Ltd. 发明人 Yeh Ching-Fu;Peng Chao-Hsien;Wu Hsien-Chang;Lee Hsiang-Huan
分类号 H01L21/4763;H01L21/768;H01L21/02;H01L23/532;H01L21/027;H01L21/3213;B82Y40/00 主分类号 H01L21/4763
代理机构 Haynes and Boone,LLP 代理人 Haynes and Boone,LLP
主权项 1. A method comprising: forming a conductive layer on a semiconductor substrate; forming a patterned material layer on the conductive layer; forming a catalyst layer on the conductive layer; forming a plurality of carbon nanotubes (CNTs) from the catalyst layer; and removing the conductive layer by using the CNTs as a mask to form conductive features.
地址 Hsin-Chu TW