LOGIC CIRCUIT AND SEMICONDUCTOR DEVICE

摘要

To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10−13 A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.

主权项

1. A semiconductor device comprising:
first to eighth transistors, first and second capacitors; wherein one of source and drain of the first transistor is electrically connected to one of source and drain of the second transistor, wherein one of source and drain of the third transistor is electrically connected to a gate of the first transistor, wherein one of source and drain of the fourth transistor is electrically connected to a gate of the second transistor, wherein a first electrode of the first capacitor is electrically connected to the gate of the second transistor, wherein a second electrode of the first capacitor is electrically connected to the other of source and drain of the second transistor, wherein one of source and drain of the fifth transistor is electrically connected to one of source and drain of the sixth transistor, wherein one of source and drain of the seventh transistor is electrically connected to a gate of the fifth transistor, wherein one of source and drain of the eighth transistor is electrically connected to a gate of the sixth transistor, wherein a first electrode of the second capacitor is electrically connected to the gate of the sixth transistor, wherein a second electrode of the second capacitor is electrically connected to the other of source and drain of the sixth transistor, wherein power supply voltage is supplied to the other of source and drain of the second transistor, wherein the power supply voltage is supplied to the other of source and drain of the sixth transistor, wherein the one of source and drain of the first transistor is electrically connected to a first output terminal, wherein the other of source and drain of the third transistor is electrically connected to a first input terminal, wherein the one of source and drain of the fifth transistor is electrically connected to a second output terminal, and wherein the other of source and drain of the seventh transistor is electrically connected to a second input terminal.