发明名称 |
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE |
摘要 |
A semiconductor device includes an element portion and a gate pad portion on the same wide gap semiconductor substrate. The element portion includes a first trench structure having a plurality of first protective trenches and first buried layers formed deeper than gate trenches. The gate pad portion includes a second trench structure having a plurality of second protective trenches and second buried layers. The second trench structure is either one of a structure where the second trench structure includes: a p-type second semiconductor region and a second buried layer made of a conductor or a structure where the second trench structure includes a second buried layer formed of a metal layer which forms a Schottky contact. The second buried layer is electrically connected with the source electrode layer. |
申请公布号 |
US2017040423(A1) |
申请公布日期 |
2017.02.09 |
申请号 |
US201515303730 |
申请日期 |
2015.07.10 |
申请人 |
SHINDENGEN ELECTRIC MANUFACTURING CO., LTD. |
发明人 |
INOUE Tetsuto;SUGAI Akihiko;NAKAMURA Shunichi |
分类号 |
H01L29/40;H01L29/66;H01L29/06;H01L29/78;H01L29/16;H01L29/10 |
主分类号 |
H01L29/40 |
代理机构 |
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代理人 |
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主权项 |
1. A semiconductor device comprising:
a wide gap semiconductor substrate; an element portion formed on the wide gap semiconductor substrate, the element portion comprising: a drift layer of a first conductive type; a body layer of a second conductive type opposite to the first conductive type, the body layer positioned over the drift layer; a gate trench formed so as to open in the body layer and to reach the drift layer; a source region of the first conductive type formed in a state where the source region is arranged in the inside of the body layer and at least a portion of the source region is exposed on an inner peripheral surface of the gate trench; a gate insulation layer formed on the inner peripheral surface of the gate trench; a gate electrode layer formed inside the gate trench by way of the gate insulation layer; and a source electrode layer formed in a state where the source electrode layer is insulated from the gate electrode layer and is brought into contact with the source region; and a gate pad portion formed on the wide gap semiconductor substrate, the gate pad portion comprising: a drift layer of the first conductive type; a second-conductive-type semiconductor layer of the second conductive type positioned on the drift layer; an insulation layer formed on the second-conductive-type semiconductor layer; and a gate line formed on the insulation layer, wherein the element portion further includes a first trench structure which has: a plurality of first protective trenches where the first protective trenches open in the body layer in a region between the gate trenches formed adjacently to each other and are formed deeper than the gate trenches; and a first buried layer formed inside the respective first protective trenches, and the gate pad portion further includes a second trench structure which has: a plurality of second protective trenches where the second protective trenches open in the second-conductive-type semiconductor layer and are formed deeper than the gate trenches; and a second buried layer formed inside the respective second protective trenches, the second trench structure is either one of a structure where the second trench structure further includes a second semiconductor region of the second conductive type formed on at least a bottom portion of the second protective trench, and includes a second buried layer which is made of a conductor as the second buried layer or a structure where the second trench structure includes a second buried layer which is formed of a metal layer forming a Schottky contact with the drift layer on a bottom portion and a side portion of the second protective trench as the second buried layer, and the second buried layer is electrically connected with the source electrode layer. |
地址 |
Chiyoda-ku, Tokyo JP |