HYBRID HARDWARE AND SOFTWARE IMPLEMENTATION OF TRANSACTIONAL MEMORY ACCESS

摘要

Embodiments of the invention relate a hybrid hardware and software implementation of transactional memory accesses in a computer system. A processor including a transactional cache and a regular cache is utilized in a computer system that includes a policy manager to select one of a first mode (a hardware mode) or a second mode (a software mode) to implement transactional memory accesses. In the hardware mode the transactional cache is utilized to perform read and write memory operations and in the software mode the regular cache is utilized to perform read and write memory operations.

主权项

1. A processor comprising:
transactional memory circuitry to process a region of transactional memory operations including load operations and store operations, the transactional memory circuitry to process a transaction begin instruction to initiate the region of transactional memory operations, a transaction end instruction to indicate an end of the region of transactional memory operations, and a transaction abort instruction to abort processing of the transactional memory operations; transaction failure detection circuitry to detect a transaction failure responsive to conflicting load and store operations, wherein a transaction failure is to be generated by data loaded by a first transaction being modified by a second transaction; a status circuit to store an indication as to whether a transaction is valid or invalid, the status circuit to set the indication to invalid upon the transaction failure; locking circuitry to allow a transaction to acquire a lock on a critical section of program code, wherein the transactional memory circuitry is to attempt to execute critical sections of instructions as transactions on multiple threads without acquiring a lock; the locking circuitry to cause the critical sections to be re-executed non-speculatively using one or more locks in response to detecting a transaction failure.