发明名称 補間回路および受信回路
摘要 An interpolation circuit includes: a plurality of holding circuits configured to each hold a corresponding input data input chronologically; and a generating circuit configured to generate interpolation data by giving weights, based on an interpolation code, to input data that are chronologically adjacent to each other and are held by the plurality of holding circuits and combining the weighted data together.
申请公布号 JP6075191(B2) 申请公布日期 2017.02.08
申请号 JP20130095982 申请日期 2013.04.30
申请人 富士通株式会社 发明人 ▲浜▼田 隆行;塚本 三六
分类号 H03M1/36;H03M1/12;H04L1/00;H04N7/01 主分类号 H03M1/36
代理机构 代理人
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