Test structure for determining overlay accuracy in semiconductor devices using resistance measurement

摘要

Provided is a test pattern structure for determining overlay accuracy in a semiconductor device. The test pattern structure includes one or more resistor structures formed by patterning a lower silicon layer. Each includes a zigzag portion with leads at different spatial locations. An upper pattern is formed and includes at least one pattern feature formed over the resistor or resistors. The portions of the resistor or resistors not covered by the upper pattern feature will become silicided during a subsequent silicidation process. Resistance is measured to determine overlay accuracy as the resistor structures are configured such that the resistance of the resistor structure is determined by the degree of silicidation of the resistor structure which is determined by the overlay accuracy between the upper and lower patterns.

主权项

1. A test pattern structure in a semiconductor device for determining pattern overlay accuracy, comprising:
a semiconductor pattern of a semiconductor material bounded by a dielectric, said semiconductor pattern including a first resistor structure and a second resistor structure; each of said first resistor structure and said second resistor structure including a zigzag portion including transverse leads, wherein said transverse leads include first transverse leads of said first resistor structure and second transverse leads of said second resistor structure, said first transverse leads parallel to said second transverse leads and said first resistor structure comprising first parallel leads orthogonal to said first transverse leads and said second resistor structure including second parallel leads orthogonal to said second transverse leads and parallel to said first parallel leads.