Effective device formation for advanced technology nodes with aggressive fin-pitch scaling

摘要

After forming a gate stack straddling a portion of each semiconductor fin of a plurality of semiconductor fins located over a substrate, a gate liner is formed on sidewalls of a lower portion of the gate stack that contacts the plurality of semiconductor fins and a gate spacer having a width greater than a width of the gate liner is formed on sidewalls of an upper portion of the gate stack that is located above the plurality of semiconductor fins. The width of the gate spacer thus is not limited by the fin pitch, and can be optimized to improve the device performance.

主权项

1. A method of forming a semiconductor structure comprising:
forming a gate stack over a portion of each of a plurality of semiconductor fins located on a substrate; forming a dielectric liner layer over exposed surfaces of the gate stack, the plurality of semiconductor fins and the substrate; forming a sacrificial dielectric portion filling spaces between the plurality of semiconductor fins; removing a portion of the dielectric liner layer from an upper portion of the gate stack that is located above the plurality of semiconductor fins to provide a dielectric liner, the dielectric liner laterally surrounding a lower portion of the gate stack that contacts the plurality of the semiconductor fins; forming a gate spacer laterally surrounding an upper portion of the gate stack that is located above the plurality of the semiconductor fins; removing the sacrificial dielectric portion; and removing portions of the dielectric liner that are not covered by the gate spacer from sidewalls of the plurality of semiconductor fins and a top surface of the substrate.