Fin field-effect transistor and fabrication method thereof

摘要

A method for fabricating a FinFET structure comprises providing a semiconductor substrate; forming a hard mask layer on the semiconductor substrate; forming a dummy gate structure having a dummy gate, a first sidewall spacer and a second sidewall spacer; removing the dummy gate to form a first trench; forming first sub-fins in the semiconductor substrate under the hard mask layer in the first trench; forming a first metal gate structure in the first trench; removing the first sidewall spacer to form a second trench; forming second sub-fins in the semiconductor substrate under the hard mask layer in the second trench; forming a second metal gate structure in the second trench; removing the second sidewall spacer to form a third trench; forming third sub-fins in the semiconductor substrate under the hard mask layer in the third trench; and forming a third metal gate structure in the third trench.

主权项

1. A method for fabricating a Fin field-effect transistor structure, comprising:
providing a semiconductor substrate; forming a hard mask layer on the semiconductor substrate; forming a dummy gate structure having a dummy gate, a first sidewall spacer and a second sidewall spacer crossing over the hard mask layer on the semiconductor substrate; wherein forming the dummy gate structure further comprises: forming a dummy gate material layer covering the hard mask layer on the semiconductor substrate; patterning the dummy gate material layer to form the dummy gate crossing over the hard mask layer; forming a sidewall spacer material layer on the semiconductor substrate, the dummy gate and the mask layer; etching the sidewall spacer material layer to form the first sidewall spacer and the second sidewall spacer on two side surfaces of the dummy gate; removing the dummy gate to form a first trench to expose the hard mask layer; forming first sub-fins in the semiconductor substrate under the hard mask layer; forming a first metal gate structure in the first trench; removing the first sidewall spacer to form a second trench to expose the hard mask layer; forming second sub-fins in the semiconductor substrate under the hard mask layer; forming a second metal gate structure in the second trench; removing the second sidewall spacer to form a third trench to expose the hard mask layer; forming third sub-fins in the semiconductor substrate under the hard mask layer; and forming a third metal gate structure in the third trench.