METHODS FOR PROGRAMMING AND ACCESSING DDR COMPATIBLE RESISTIVE CHANGE ELEMENT ARRAYS

摘要

A high-speed memory circuit architecture for arrays of resistive change elements is disclosed. An array of resistive change elements is organized into rows and columns, with each column serviced by a word line and each row serviced by two bit lines. Each row of resistive change elements includes a pair of reference elements and a sense amplifier. The reference elements are resistive components with electrical resistance values between the resistance corresponding to a SET condition and the resistance corresponding to a RESET condition within the resistive change elements being used in the array. A high speed READ operation is performed by discharging one of a row's bit lines through a resistive change element selected by a word line and simultaneously discharging the other of the row's bit lines through of the reference elements and comparing the rate of discharge on the two lines using the row's sense amplifier. Storage state data are transmitted to an output data bus as high speed synchronized data pulses. High speed data is received from an external synchronized data bus and stored by a PROGRAM operation within resistive change elements in a memory array configuration.

主权项

1. A method of reading the informational state of a resistive change element, said method comprising:
providing a resistive change element, wherein said resistive change element is capable of being switched between at least two non-volatile resistance values with a first resistance value corresponding to a first informational state and a second resistance value corresponding to a second informational state; providing a resistive reference element, wherein said resistive reference element has an electrical resistance selected to fall between said first resistance value and said second resistance value; discharging a voltage through both said resistive change element and said resistive reference element; and comparing the rate of discharge through said resistive change element to the rate of discharge through said resistive reference element; wherein a greater rate of discharge through said resistive change element corresponds to a first informational state being stored within said resistive change element and a greater rate of discharge through said resistive reference element corresponds to a second informational state being stored within said resistive change element.