发明名称 SEAMLESS ADDITION OF HIGH BANDWIDTH LANES
摘要 Seamless addition of high bandwidth lanes, including the steps of: sending, by a master, an idle sequence using 7b/10b code words over new high bandwidth lanes in parallel to sending and receiving 8b/10b data with a fixed delay over master-to-slave (m2s) and slave-to-master (s2m) active high bandwidth lanes; sending in parallel a synchronization sequence and a known non-idle sequence during an inter packet gap; utilizing, by the slave, the known non-idle sequence for deskewing the new high bandwidth lanes; and sending, by the master, a transition sequence over both the m2s active high bandwidth lane and the new high bandwidth lanes, and immediately thereafter the master is ready to transmit high bandwidth data using 8b/10b code words over both the m2s active high bandwidth lane and the new high bandwidth lanes.
申请公布号 WO2017017562(A1) 申请公布日期 2017.02.02
申请号 WO2016IB54296 申请日期 2016.07.19
申请人 VALENS SEMICONDUCTOR LTD. 发明人 LIDA, Eyran;SALAMON, Aviv
分类号 G06F13/42 主分类号 G06F13/42
代理机构 代理人
主权项
地址