发明名称 MEMORY SYSTEM AND MEMORY CONTROL METHOD
摘要 According to one embodiment, a memory system includes: a non-volatile memory; a memory interface that reads a received word from the non-volatile memory; a decoder that decodes the received word; a control unit that predicts the number of error bits in the received word read from the non-volatile memory, predicts decoding time on the basis of the number of error bits predicted, and determines an operating clock frequency of the decoder on the basis of the predicted decoding time and requested decoding time being the decoding time requested; and a frequency control unit that supplies the operating clock frequency determined by the control unit to the decoder and supplies voltage corresponding to the operating clock frequency being determined to the decoder.
申请公布号 US2017031755(A1) 申请公布日期 2017.02.02
申请号 US201615065092 申请日期 2016.03.09
申请人 Kabushiki Kaisha Toshiba 发明人 NAKANISHI Yu;IWAI Daisuke;WATANABE Kiwamu;FUNAOKA Kenji;SUNATA Tetsuya;HARA Keigo;TAKADA Marie
分类号 G06F11/10;G11C7/22;G11C29/52 主分类号 G06F11/10
代理机构 代理人
主权项 1. A memory system comprising: a non-volatile memory; a memory interface that reads a received word from the non-volatile memory; at least one decoder that decodes the received word; a control unit that predicts the number of error bits in the received word read from the non-volatile memory, predicts a decoding time on a basis of the number of error bits predicted, and determines an operating clock frequency of the decoder on a basis of the predicted decoding time and a requested decoding time; and a frequency control unit that supplies the operating clock frequency determined by the control unit to the decoder and supplies voltage corresponding to the operating clock frequency determined by the control unit to the decoder.
地址 Minato-ku JP