| 摘要 |
A clock delay circuit, comprising: a control module (102) and at least one stage of delay module (101). The delay module (101) is configured to perform a delay. Two output terminals of each stage of the delay module (101) are respectively connected to two input terminals of the next stage of the delay module (101). The two output terminals of each stage of the delay module (101) are respectively connected to two input terminals of the control module (102). The control module (102) is configured to select two output terminals of a certain stage of the delay module (101) as two output terminals of the clock delay circuit according to the required delay. The clock delay circuit no longer only produces a single delay time, but may produce a plurality of delay times, thereby achieving the purpose of adjustable delay time. |
