发明名称 3レベルインバータのスナバ回路
摘要 PROBLEM TO BE SOLVED: To provide a snubber circuit for a three-level inverter capable of ensuring a surge absorbing operation of a snubber capacitor by suppressing voltage increase of the snubber capacitor.SOLUTION: Between a positive electrode end P and a negative electrode end N of a DC power supply circuit, a main circuit switch P-side element Tr1 and a main circuit switch N-side element Tr4 are connected in series and between a neutral point M of the DC power supply circuit and an AC input/output end AC, main circuit switch neutral point clamp elements Tr2 and Tr3 are connected in series. As a snubber circuit of Tr1, a snubber capacitor C1, a sub switch S1 and a reverse block diode d1 connected in series between P and AC and a snubber resistor R1 connected between a common connection point of C1 and S1 and M are provided. As a snubber circuit of Tr4, a snubber capacitor C4, a sub switch S4 and a reverse block diode d4 which are connected in series between N and AC, and a snubber resistor R4 connected between a common connection point of C4 and S4 and M are provided.
申请公布号 JP6070258(B2) 申请公布日期 2017.02.01
申请号 JP20130032771 申请日期 2013.02.22
申请人 株式会社明電舎 发明人 渡瀬 祐樹
分类号 H02M7/487;H02M7/48 主分类号 H02M7/487
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