Semiconductor device

摘要

In a semiconductor device, memory modules each having a low power consumption mode that is enabled and disabled by a control signal belong to a memory block. A transmission path of the control signal is provided such that the control signal is inputted in parallel to the memory module via an inside-of-module path, and such that the control signal is outputted by a particular memory module of the memory modules via the inside-of-module path to a downstream outside-of-module path. The particular memory module in the memory block is selected such that it has a greater storage capacity than the other memory modules belonging to this same memory block have.

主权项

1. A semiconductor device comprising:
a central processing unit that executes a command; a memory disposed in a memory space of the central processing unit and coupled to receive a control signal from the central processing unit, the memory including:
a first memory module,a second memory module,a third memory module, anda fourth memory module,each of the memory modules having a memory cell array including memory cells and a peripheral circuit that performs reading and writing of data to or from the memory cells,each of the memory modules having a standby mode to consume less electric power than in a normal operation mode in which reading or writing to or from the memory cells is performed; a first control signal line coupled to the first memory module and the second memory module to transmit the control signal for controlling the normal operation mode and the standby mode in parallel to the first memory module and the second memory module; a second control signal line coupled to the third memory module and the fourth memory module to transmit the control signal to the third memory module and the fourth memory module via the first memory module; and a first wiring disposed in the first memory module and coupled between the first control signal line and the second control signal line to transmit the control signal from the first control signal line to the second control signal line via the first wiring, wherein the first memory module has a greater number of memory cells than the second memory module.